The present disclosure relates generally to microelectromechanical system (MEMS) technology and more specifically to fabrication of MEMS devices using complementary-metal-oxide-semiconductor (CMOS) compatible processes.
A variety of monolithic (e.g., single substrate) CMOS-MEMS integration methods have been studied as providing benefits for integrating CMOS and MEMS devices onto a single substrate, such as for system-on-chip (SOC) devices. The integration may provide for lower parasitics (e.g., resistance, inductance, and capacitance), lower cost, and/or increased performance. One approach developed for the integration of CMOS and MEMS devices and processes includes formation of a CMOS device using typical processing and then forming the MEMS device. In the approach, during the MEMS formation, the backside of a substrate (e.g., wafer) is processed (e.g., bulk micromachining) followed by processing on the front-side of the substrate (e.g., surface micromachining). Though this approach purports to create advantages in not damaging the MEMS device by subsequent processing, it also includes disadvantages. The approach, as well as other conventional fabrication processes, requires substantial handling of the wafers (e.g., numerous taping, de-taping processes) to form the final device. Such handling may introduce risks of substrate breakage, glue layer degradation, and/or other possible defects. Conventional approaches also may require etch stop layers to be used when etching the backside of the substrate (e.g., bulk micromachining) requiring additional considerations of etch selectivity, post-etching surface roughness issues, and/or other possible issues.
Therefore, what is needed is an improved method of integrated CMOS-MEMS fabrication.